temperature range, otherwise specifi cations are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are relative to VSS unless otherwise noted. (Note 2, Note 5)PARAMETERVDD5 Supply VoltageVDD5 Internal Supply VDD48 Supply CurrentVDD5 Supply CurrentOn-ResistanceOUT Pin LeakageOUT Pin Pull-Up Resistance to VDD48Overload Current ThresholdCONDITIONSDriven ExternallyDriven InternallyVDD5 – VSS = 5VInternal VDD5VDD5 – VSS = 5VI = 350mA, Measured From OUT to VSSVOUT – VSS = VDD48 – VSS = 57V 0V ≤ (VDD48 – VOUT) ≤ 5V Class 0, Class 3, Class 4 (Note 6)Class 2Class 1VOUT – VSS = 5VVDD48 – VOUT = 30V VDD48 – VOUT = 0V (Note 7)VDD48 – VOUT = 10V (Note 8)●●●●●MIN4.54.3TYP54.41211.5136035516595405405301105.2500500375175100425425601407.5650MAX5.54.52422.43.01003951851054454451201809.8800UNITSVVmAmAmAΩΩµAkΩmAmAmAmAmAmAmAmAmAPower MOSFET●●●●●●●●●●●●Current ControlShort-Circuit Current LimitFoldback Current Limit DC Disconnect Current ThresholdHigh-Speed Fault Current LimitClassifi cationPower ManagementVPWRMGTIPWRMGTPower Management Pin ThresholdPower Management Pin Output CurrentAC DisconnectROSCIOSCFOSCAVACDOSC Pin Input ImpedanceOSC Pin Output CurrentOSC Pin FrequencyVoltage Gain OSC to ACOUT3
LTC4263ELECTRICAL CHARACTERISTICS The ● denotes the specifi cations which apply over the full operating SYMBOLIACDMAXIACDMINVACDENVOLEDVILDVIHDVOZIOLEGIFLTPARAMETERAC Disconnect Output CurrentRemain Connected AC Pin CurrentAC Disconnect Enable SignalLED Output Low VoltageDigital Input Low VoltageDigital Input High VoltageVoltage of Legacy Pin if Left FloatingCurrent In/Out of Legacy PinMaximum Allowed Leakage of External Components at Legacy Pin in Force Power-On ModeDetection TimeDetection DelayClassifi cation DurationPower Turn-On DelayTurn-On Rise Time Overload/Short-Circuit Time LimitError DelayMPS Minimum Pulse WidthMidspan Mode Detection BackoffPower Removal Detection DelayICUT Fault to Next DetectPD Minimum Current Pulse Width Required to Stay Connected (Note 11)RPORT = 15.5kΩMaintain Power Signature (MPS) Disconnect DelayPD Removal to Power RemovalVDD48 – VOUT: 10% to 90%CPSE = 0.1µFBeginning to End of DetectionPD Insertion to Detection Complete0V ≤ (VLEGACY – VSS) ≤ 5V CONDITIONSVOSC – VSS = 2V, 0V ≤ (VACOUT – VSS) ≤ 4VVOSC – VSS = 2VVOSC – VSS, Port OnILED = 10mAMIDSPAN, PWRMGT, ENFCLS, SDLEGACYMIDSPAN, PWRMGT, ENFCLS, SDLEGACY●●●temperature range, otherwise specifi cations are at TA = 25°C. VDD48 – VSS = 48V and VDD5 not driven externally. All voltages are relative to VSS unless otherwise noted. (Note 2, Note 5)MIN–11301.51.12.20.80.42.22.21.1–60–101.251.46010TYP160MAX190UNITSmAµAVVVVVVµAµA 1Digital Interface (Note 10)●●●●●●●●Timing CharacteristicstDETtDETDLYtPDCtPONtRISEtOVLDtEDtMPDOtMPStDBOtDISDLY●●●2703003413540523.832029037145170624.035031062039155msmsmsmsµsEnd of Valid Detect to Application of Power●●●●●●●●724.238020mssmsmsss3.00.83.20.953.41.1Note 1: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. Exposure to any Absolute Maximum Rating condition for extended periods may affect device reliability and lifetime.Note 2: All currents into device pins are positive; all currents out of device pins are negative. All voltages are referenced to VSS unless otherwise specifi ed. Note 3: 80mA of current may be pulled from the OUT or ACOUT pin without damage whether the LTC4263 is powered or not. These pins will also withstand a positive voltage of VSS +80V.Note 4: This IC includes overtemperature protection that is intended to protect the device during momentary overload conditions. Junction temperature will exceed 125°C when overtemperature protection is active. Continuous operation above the specifi ed maximum operating junction temperature may impair device reliability.Note 5: The LTC4263 operates with a negative supply voltage. To avoid confusion, voltages in this data sheet are referred to in terms of absolute magnitude. Note 6: If the ENFCLS pin is high, ICUT depends on the result of cation.classifi cation. If ENFCLS pin is low, ICUT reverts to its Class 0 specifiNote 7: In order to reduce power dissipated in the switch while charging the PD, the LTC4263 reduces the current limit when VOUT – VSS is large. Refer to the Typical Performance Characteristics for more information.Note 8: The LTC4263 includes a high-speed current limit circuit intended to protect against faults. The fault protection is activated for port current in excess of IFAULT. After the high-speed current limit activates, the short-circuit current limit (ILIM) engages and restricts current to IEEE 802.3af levels.Note 9: Class 4 or higher classifi cation current is treated as Class 3.Note 10: The LTC4263 digital interface operates with respect to VSS. All logic levels are measured with respect to VSS.Note 11: The IEEE 802.3af specifi cation allows a PD to present its Maintain Power Signature (MPS) on an intermittent basis without being disconnected. In order to stay powered, the PD must present the MPS for tMPS within any tMPDO time window.4263fb
4
LTC4263TYPICAL PERFORMANCE CHARACTERISTICSPowering an IEEE 802.3af PDVDD48DETECTIONDETECTIONVOUTPHASE 1PHASE 210V/DIVCLASSIFICATIONVSSPOWERONVDD48VOUT20V/DIVVSS425mA CURRENT LIMIT400mAFOLDBACKIOUTCLASSIFICATION200mA/DIV0mA4263 G01Powering a Legacy PD with 220µF Bypass CapacitorVOUT2V/DIVVDD48 – 18VVDD48 – 19V40mAIOUT20mA/DIV0mAClassifi cation Transient Response to 40mA Load StepVDD48 – VSS = 48VTA = 25°CLOADFULLYCHARGED100ms/DIV25ms/DIV4263 G02100µs/DIV4263 G06Overload Restart DelayVDD48tEDVOUT10V/DIVVOUT2V/DIVVDD48Midspan Backoff with Invalid PD tDBOVDD48VOUT20V/DIVVSS400mAIOUT200mA/DIV0mA500ms/DIV4263 G11Overcurrent Response TimePORT OFFVSSIPORT500mA/DIV500ms/DIVRPORT = 15.5kΩ4263 G10tOVLDLOADAPPLIED10ms/DIV4263 G12Response to PD Removal with AC Disconnect EnabledVDD48VDD48VOUT20V/DIVVSSPD REMOVALVSStMPDO50ms/DIV4263 G13Rapid Response to 1Ω ShortVDD48VOUT20V/DIVIPORT = CURRENT IN 1Ω RESISTOR APPLIED TO OUTPUT OF CIRCUITON FRONT PAGEVSS800mAIPORT400mA/DIV0mARapid Response to Momentary 50Ω ShortVOUT10V/DIVPORT OFF50Ω SHORT APPLIEDIPORT20A20A/DIV0A1Ω SHORT APPLIEDSHORTCURRENT REMOVEDLIMIT ACTIVEFOLDBACK CURRENT LIMIT1µs/DIV4263 G14100µs/DIV4263 G15IPORT = CURRENT IN 50Ω RESISTOR APPLIED TO OUTPUT OF CIRCUIT ON FRONT PAGE4263fb5LTC4263TYPICAL PERFORMANCE CHARACTERISTICSCurrent Limit and Foldback450400VLED PIN PULLDOWN (V)350300IOUT (mA)25020015010050005101520253035404550VDD48 – VOUT4263 G03LED Pin Pulldown vs Load Current4TA = 25°CINTERNAL VDD5807060IOUT (mA)50403020100010203040ILED LOAD CURRENT (mA)504263 G04Classifi cation Current ComplianceVDD48 – VSS = 48VTA = 25°C32100412VDD48 – VOUT (V)816204263 G05IDD48 DC Supply Current vs Supply Voltage with Internal VDD52.5TA = 25°C1.225k LOAD WITH AC ENABLED1.00.8IDD48 (mA)IDD48 (mA)IDD48 DC Supply Current vsSupply Voltage with VDD5 = 5.0VTA = 25°C225k LOAD WITH AC ENABLEDIDD5 DC Supply Current vs Supply VoltageVDD48 = 48V25k LOAD WITH AC ENABLEDNO LOAD2.01NO LOAD0.60.4NO LOAD1.0IDD5 (mA)1.50–10.50.20010203040VDD48 (V)50604263 G07–20–3010203040VDD48 (V)50604263 G084.04.55.0VDD55.56.04263 G09RON vs Temperature2.040Legacy Pin Current vs Voltage1.8LEGACY MODE20ILEGACY (µA)RON (Ω)1.60FORCE POWER ON MODE1.41.2–20COMPLIANT MODE–401.0–40–204020060TEMPERATURE (°C)801000132VLEGACY (V)454263 G174263 G1263fb6LTC4263TEST TIMINGPDINSERTEDVDD48tDETVOUTVCLASStPDCtDETDLYtPON4263 TT01ILIMIOUTPORT TURN-ON VDD48VOUTVSSICUTtOVLD4263 TT02Detect, Class and Turn-On TimingCurrent Limit TimingVOSCVDD48IOUTVOUTVSSIMINVDD48VOUTVSStMPStMPDO4263 TT03IACOUTIACDMINPD REMOVEDtMPDO4263 TT04DC Disconnect TimingAC Disconnect Timing4263fb7LTC4263PIN FUNCTIONS
(DFN/SO)LED (Pin 1): Port State LED Drive. This pin is an open drain output that pulls down when the port is powered. Under port fault conditions, the LED will fl ash in patterns to indicate the nature of the port fault. See the Applications Informa-tion section for a description of these patterns. When the LTC4263 is operated from a single 48V supply, this pin is pulsed low with a 6% duty cycle during the periods when the LED should be on. This allows use of a simple inductor, diode, and resistor circuit to avoid excess heating due to the large voltage drop from VDD48. See the Applications Information section for details on this circuit. LEGACY (Pin 2): Legacy Detect. This pin controls whether legacy detect is enabled. If held at VDD5, legacy detect is enabled and testing for a large capacitor is performed to detect the presence of a legacy PD on the port. See the Applications Information section for descriptions of legacy PDs that can be detected. If held at VSS, only IEEE 802.3af compliant PDs are detected. If left fl oating, the LTC4263 enters force-power-on mode and any PD that generates between 1V and 10V when biased with 270µA of detection current will be powered as a legacy device. This mode is useful if the system uses a differential detection scheme to detect legacy devices. Warning: Legacy modes are not IEEE 802.3af compliant.MIDSPAN (Pin 3): Midspan Enable. If this pin is connected to VDD5, Midspan backoff is enabled and a 3.2 second delay occurs after every failed detect cycle unless the result is open circuit. If held at VSS, no delay occurs after failed detect cycles. PWRMGT (Pin 4): Power Management. The LTC4263 sources current at the PWRMGT pin proportional to the class of the PD that it is powering. The voltage of this pin is checked before powering the port. The port will not turn on if this pin is more than 1V above VSS. Connect the PWRMGT pins of multiple LTC4263s together with a resis-tor and capacitor to VSS to implement power management. If power management is not used, tie this pin to VSS.VSS (Pins 5, 6): Negative 48V Supply. Pins 5 and 6 should be tied together on the PCB.OSC (Pin 7) Oscillator for AC Disconnect. If AC discon-nect is used, connect a 0.1µF X7R capacitor from OSC to VSS. Tie OSC to VSS to disable AC disconnect and enable DC disconnect.ACOUT (Pin 8): AC Disconnect Sense. Senses the port to determine whether a PD is still connected when in AC disconnect mode. If port capacitance drops below about 0.15µF for longer than TMPDO the port is turned off. If AC disconnect is used, connect this pin to the port with a series combination of a 1k resistor and a 0.47µF 100V X7R capacitor. See the Applications Information section for more information.OUT (Pins 9, 10): Port Output. If DC disconnect is used, these pins are connected to the port. If AC disconnect is used, these pins are connected to the port through a parallel combination of a 1A diode and a 500k resistor. Pins 9 and 10 should be tied together on the PCB. See the Applications Information section for more information.VDD48 (Pin 11): 48V Return. Must be bypassed with a 0.1µF capacitor to VSS. SD (Pin 12): Shutdown. If held low, the LTC4263 is pre-vented from performing detection or powering the port. Pulling SD low will turn off the port if it is powered. When released, a 4-second delay will occur before detection is attempted.ENFCLS (Pin 13): Enforce Class Current Limits. If held at VDD5, the LTC4263 will reduce the ICUT threshold for class 1 or class 2 PDs. If ENFCLS is held at VSS, ICUT remains at 375mA (typ) for all classes.VDD5 (Pin 14): Logic Power Supply. Apply 5V referenced to VSS, if such a supply is available, or place a 0.1µF bypass capacitor to VSS to enable the internal regulator. When the internal regulator is used, this pin should only be connected to the bypass capacitor and to any logic pins of the LTC4263 that are being held at VDD5.Exposed Pad (Pin 15, DE Package Only): VSS. Must be connected to VSS on the PCB. The exposed pad acts as a heatsink for the internal MOSFET.4263fb
8
LTC4263BLOCK DIAGRAM1AVDD4812SD14RLEDVDD5VDD5INT5 EXT55V REG13ENFCLS2LEGACY3MIDSPAN1LED4TO PORTMAGNETICS0.1µF11+48V–CONTROLTO OTHER LTC4263s4PWRMGT500k+5VSMAJ58AHOT SWAPIDET–CPMRPM560.1µF9VSS10OUT500k0.47µF1k7OSC8ACOUT4263 BDBOLD LINES INDICATE HIGH CURRENT4263fb9LTC4263APPLICATIONS INFORMATIONPOE OVERVIEWOver the years, twisted-pair Ethernet has become the most commonly used method for local area networking. The IEEE 802.3 group, the originator of the Ethernet standard, has defi ned an extension to the standard, IEEE 802.3af, which allows DC power to be delivered simultaneously over the same cable used for data communication. This has enabled a whole new class of Ethernet devices, in-cluding IP telephones, wireless access points, and PDA charging stations which do not require additional AC wiring or external power transformers, a.k.a. “wall warts.” With about 13W of power available, small data devices can be powered by their Ethernet connections, free from AC wall outlets. Sophisticated detection and power mon-itoring techniques prevent damage to legacy data-only devices while still supplying power to newer, Ethernet-powered devices over the twisted-pair cable.The device that supplies power is called the Power Sourc-ing Equipment (PSE). A device that draws power from the wire is called a Powered Device (PD). A PSE is typically an Ethernet switch, router, hub, or other network switching equipment that is commonly found in the wiring closets where cables converge. PDs can take many forms. Digital IP telephones, wireless network access points, PDA or notebook computer docking stations, cell phone chargers, CAT 520Ω MAXROUNDTRIP0.05µF MAXand HVAC thermostats are examples of devices that can draw power from the network.A PSE is required to provide a nominal 48V DC between either the signal pairs or the spare pairs (but not both) as shown in Figure 1. The power is applied as a voltage between two of the pairs, typically by powering the cen-ter taps of the isolation transformers used to couple the differential data signals to the wire. Since Ethernet data is transformer coupled at both ends and is sent differen-tially, a voltage difference between the transmit pairs and the receive pairs does not affect the data. A 10Base-T/100Base-TX Ethernet connection only uses two of the four pairs in the cable. The unused or spare pairs can option-ally be powered directly, as shown in Figure 1, without affecting the data. 1000Base-T uses all four pairs and power must be connected to the transformer center taps if compatibility with 1000Base-T is required.The LTC4263 provides a complete PSE solution for de-tection and powering of PD devices in an IEEE 802.3af compliant system. The LTC4263 controls a single PSE port that will detect, classify, and provide isolated 48V power to a PD device connected to the port. The LTC4263 senses removal of a PD with IEEE 802.3af compliant AC or DC methods and turns off 48V power when the PD is disconnected. An internal control circuit takes care of system confi guration and timing.PSERJ4545RJ4545PD–48V RETURN0.1µF0.1µFVDD48TxSPARE PAIR11Rx2LTC4263VDD50.1µFSMAJ58A58V–48V SUPPLYVSSOUT76SPARE PAIR763Rx6DATA PAIR63TxDATA PAIR21N4002×4SMAJ58A58V5µF ≤ CIN≤ 300µF0.1µF1N4002×4GNDRCLASSLTC4267-BASEDOUTPD/SWITCHER–48VIN–48VOUT+VOUT–4263 F01Figure 1. System Diagram4263fb10LTC4263APPLICATIONS INFORMATIONLTC4263 OPERATIONSignature DetectionThe IEEE 802.3af specifi cation defi nes a specifi c pair-to-pair signature resistance used to identify a device that can accept power via its Ethernet connection. When the port voltage is below 10V, an IEEE 802.3af compliant PD will have an input resistance of approximately 25kΩ. Figure 2 illustrates the relationship between the PD sig-nature resistance and the required resistance ranges the PSE must accept and reject. According to the IEEE 802.3af specifi cation, the PSE must accept PDs with signatures between 19kΩ and 26.5kΩ and may or may not accept resistances in the two ranges of 15kΩ to 19kΩ and 26.5kΩ to 33kΩ. The black box in Figure 2 represents the typical 150Ω pair-to-pair termination used in Ethernet devices like a computer’s network interface card (NIC) that cannot accept power.RESISTANCE0Ω10k20k30ka test current into the port, waiting a short time to allow the line to settle and measuring the resulting voltage. This result is stored and the second current is applied to the port, allowed to settle and the voltage measured.CURRENT (µA)25525kΩ SLOPE180VALID PDFIRSTDETECTIONPOINTSECONDDETECTIONPOINT0V-2VOFFSETVOLTAGE4263 F03Figure 3. PD Two-Point Detection23.75k26.25kPDPSE150Ω (NIC)REJECT15k19kACCEPT26.5kREJECT33k4263 F02The LTC4263 will not power the port if the PD has more than 5µF in parallel with its signature resistor unless legacy mode is enabled.The LTC4263 autonomously tests for a valid PD connected to the port. It repeatedly queries the port every 580ms, or every 3.2s if midspan backoff mode is active (see below). If detection is successful, it performs classifi cation and power management and then powers up the port.Midspan BackoffIEEE 802.3af requires the midspan PSE to wait two seconds after a failed detection before attempting to detect again unless the port resistance is greater than 500kΩ. This requirement is to prevent the condition of an endpoint PSE and a midspan PSE, connected to the same PD at the same time, from each corrupting the PD signature and prevent-ing power-on. After the fi rst corrupted detection cycle, the midspan PSE waits while the endpoint PSE completes detection and turns the port on. If the midspan mode of the LTC4263 is enabled by connecting the MIDSPAN pin to VDD5, a 3.2 second delay occurs after every failed detect cycle unless the result is an open circuit.Figure 2. IEEE 802.3af Signature Resistance RangesThe LTC4263 checks for the signature resistance by forcing two test currents on the port in sequence and measur-ing the resulting voltages. It then subtracts the two V-I points to determine the resistive slope while removing voltage offset caused by any series diodes or current offset caused by leakage at the port (see Figure 3). The LTC4263 will typically accept any PD resistance between 17kΩ and 67kΩ as a valid PD. Values outside this range (excluding open and short-circuits) are reported to the user by a code fl ashed via the LED pin.The LTC4263 uses a force-current detection method in order to reduce noise sensitivity and provide a more robust detection algorithm. The fi rst test point is taken by forcing 4263fb11LTC4263APPLICATIONS INFORMATIONClassifi cationAn IEEE 802.3af PD has the option of presenting a clas-sifi cation signature to the PSE to indicate how much power it will draw when operating. This signature consists of a specifi c constant-current draw when the PSE port volt-age is between 15.5V and 20.5V, with the current level 6050403020100PSE LOAD OVERLINECURRENT48mACURRENT (mA)CLASS 4CLASS 333mA23mATYPICALCLASS 3PD LOADLINE05CLASS 214.5mACLASS 1CLASS 06.5mA20254263 F04indicating the power class to which the PD belongs. Per the IEEE 802.3af specifi cation, there are fi ve classes and three power levels for a PD as shown in Table 1. Note that class 4 is presently reserved by the IEEE for future use. Figure 4 shows an example PD load line, starting with the shallow slope of the 25k signature resistor below 10V, then drawing the classifi cation current (in this case, class 3) between 15.5V and 20.5V. Also shown is the load line for the LTC4263. It maintains a low impedance until reaching current limit at 60mA (typ).The LTC4263 will classify a port immediately after a successful detection. It measures the PD classifi cation signature current by applying 18V (typ) to the port and measuring the resulting current. The LTC4263 identifi es the three IEEE power levels and stores the detected class internally for use by the power management circuitry. In addition, the LTC4263 allows selectable enforcement of IEEE classifi cation power levels. With the ENFCLS pin high, the LTC4263 reduces the ICUT current threshold if it detects class 1 or class 2, thereby insuring that PDs which violate their advertised class are shut down.1015VDD48 – VOUTFigure 4. Classifi cation Load LinesTable 1. IEEE 802.3af Classifi cation, PD Power Consumption, and LTC4263 Enforced Power OutputIEEE 802.3af CLASS01234CLASSIFICATION CURRENT0mA to 5mA8mA to 13mA16mA to 21mA25mA to 31mA35mA to 45mAMAXIMUMIEEE ALLOWABLE PD POWER12.95W3.84W6.49W12.95W12.95WLTC4263 ENFORCED ICUT THRESHOLD*375mA (typ)100mA (typ)175mA (typ)375mA (typ)375mA (typ)Low Power PDMedium Power PDFull Power PDReserved, Power as Class 0CLASS DESCRIPTIONPD Does Not Implement Classifi cation, Unknown Power*Enforced ICUT active if ENFCLS pin is high. Otherwise, ICUT is 375mA (typ).4263fb12LTC4263APPLICATIONS INFORMATIONPower ManagementThe LTC4263 includes a power management feature allowing simple implementation of power management across multiple ports driven by a single power supply. The PWRMGT pins of all LTC4263 devices are tied together along with an RC network to prevent over-allocation of power in a multi-port system.Immediately following classifi cation, the LTC4263 performs a power management check to ensure power is available to supply the newly classed PD. The allocated power is represented by the voltage on the shared PWRMGT node and the LTC4263 checks the allocated power by measur-ing this voltage. If the PWRMGT voltage is less than 1V, there is power available and the power needs of the new PD are added to the already allocated power on the node. To allocate power, a current proportional to the power needs for the new PD is sourced out of the PWRMGT pin (Table 2).Table 2. LTC4263 Power ManagementIEEE 802.3af CLASS0, 3, 421PSE OUTPUTPOWER REQUIRED15.4W7W4WLTC4263 PWRMGT CURRENT–72.3µA–32.8µA–18.8µAPWRMGTLTC4263VSSPWRMGTCPM =1µFLTC4263VSS4263 F05For multiple LTC4263s implementing power management, the PWRMGT pins are connected together and to a RC network connected to VSS as shown in Figure 5. The value of RPM represents the full load output capability of the system power supply (PFULL_LOAD). Select a 1% resistor to set the full load output power using the following formula:RPM= 213kΩ•WPFULL_LOADThe LTC4263 power management uses pulse width modulation to set the power requirements of each PD. lter to generate the Capacitor CPM is used as a lowpass fiaverage power requirement for all PDs in the system. Set CPM to 1µF.If power management is not used, tie PWRMGT to VSS.PWRMGTLTC4263VSSPWRMGTLTC4263VSSWhen additional current is added to the PWRMGT node, the voltage rises toward the 1V threshold. After adding current, the LTC4263 verifi es that the power supply is not over-allocated by verifying the node voltage remains below 1V. If the voltage is below 1V, the LTC4263 proceeds to power the port. If over 1V, the current is removed from the node, port powering is aborted, and the LTC4263 goes back into detection mode.RPMVSSFigure 5. PWRMGT Pin Connections4263fb13LTC4263APPLICATIONS INFORMATIONPower ControlThe primary function of the LTC4263 is to control the delivery of power to the PSE port. In order to meet IEEE 802.3af requirements and provide a robust solution, a variety of current limit and current monitoring functions are needed, as shown in Figure 6. All control circuitry is integrated and the LTC4263 requires no external MOSFET, sense resistor, or microcontroller to achieve IEEE compliance.The LTC4263 includes an internal MOSFET for driving the PSE port. The LTC4263 drives the gate of the internal MOSFET while monitoring the current and the output volt-age at the OUT pin. This circuitry couples the 48V input supply to the port in a controlled manner that satisfi es the PD’s power needs while minimizing disturbances on the 48V backplane. ment. IINRUSH refers to current at port turn-on and ILIM is the maximum allowable current in the case of a short after the port is powered. Because the IEEE specifi cation calls out identical values, the LTC4263 implements both as a single current limit referred to as ILIM.When 48V power is applied to the port, the LTC4263 is designed to power-up the PD in a controlled manner without causing transients on the input supply. To accomplish this, the LTC4263 implements inrush current limit. At turn-on, current limit will allow the port voltage to quickly rise until the PD reaches its input turn-on threshold. At this point, the PD begins to draw current to charge its bypass capacitance, slowing the rate of port voltage increase.If at any time the port is shorted or an excessive load is applied, the LTC4263 limits port current to avoid a haz-ardous condition. The current is limited to ILIM for port voltages above 30V and is reduced for lower port voltages (see the Foldback section). Inrush and short-circuit cur-rent limit are allowed to be active for 62ms (typ) before the port is shut off.Port FaultNORMALOPERATION500mAPORT CURRENT400mA300mA200mA100mA0mADC DISCONNECTCUT(ICUT)(IMIN)LIMIT(ILIM)DC DISCONNECTPORT OFF IN tMPDO4263 F07CURRENT LIMITPORT OFF IN tOVLDFigure 6. Current Thresholds and Current LimitsPort OverloadA PSE port is permitted to supply up to 15.4W continu-ously and up to 400mA (ICUT) for up to 75ms (tOVLD) when in overload. Per the IEEE 802.3af specifi cation, the PSE is required to remove power if a port stays in an overload condition. The LTC4263 monitors port current and removes port power if port current exceeds 375mA (typ) for greater than 62ms (typ).Port Inrush and Short-CircuitThe IEEE 802.3af standard lists two separate maximum current limits, IINRUSH and ILIM, that a PSE must imple-Hot Swap is a trademark of Linear Technology Corporation. If the port is suddenly shorted, the internal MOSFET power dissipation can rise to very high levels until the short-circuit current limit circuit can respond. A separate high-speed current limit circuit detects severe fault conditions (IOUT > 650mA (typ)) and quickly turns off the internal MOSFET if such an event occurs. The circuit then limits current to ILIM while the tOVLD timer increments. During a short-circuit, ILIM will be reduced by the foldback circuitry.tOVLD TimingFor overload, inrush, and short-circuit conditions, the IEEE 802.3af standard limits the duration of these events to 50ms-75ms. The LTC4263 includes a 62ms (typ) tOVLD timer to monitor overload conditions. The timer is incre-mented whenever current greater than ICUT fl ows through the port. If the current is still above ICUT when the tOVLD timer expires, the LTC4263 will turn off power to the port and fl ash the LED. In this situation, the LTC4263 waits four seconds and then restarts detection. If the overload 4263fb14LTC4263APPLICATIONS INFORMATION
condition is removed before the tOVLD timer expires, the port stays powered and the timer is reset. FoldbackFoldback is designed to limit power dissipation in the LTC4263 during power-up and momentary short-circuit conditions. At low port output voltages, the voltage across the internal MOSFET is high, and power dissipa-tion will be large if signifi cant current is fl owing. Foldback monitors the port output voltage and reduces the ILIM current limit level for port voltages of less than 28V, as shown in Figure 7.500
power and shuts down all functions including the internal 5V regulator. Once the die cools, the LTC4263 waits four seconds, then restarts detection.DC DisconnectThe DC disconnect circuit monitors port current whenever power is on to detect continued presence of the PD. IEEE 802.3af mandates a minimum current of 10mA that the PD must draw for periods of at least 75ms with optional dropouts of no more than 250ms. The tMPDO disconnect timer increments whenever port current is below 7.5mA (typ). If the timer expires, the port is turned off and the LTC4263 waits 1.5 seconds before restarting detection. If the undercurrent condition goes away before tMPDO (350ms (typ)), the timer is reset to zero. The DC discon-nect circuit includes a glitch fi lter to prevent noise from falsely resetting the timer. The current must be present for a period of at least 20ms to guarantee reset of the timer. To enable DC disconnect, tie the OSC pin to VSS.AC Disconnect400
ILIM (mA)300
200
100
0
05
101520253035404550
VDD48 – VOUT (V)
4263 F07
Figure 7. Current Limit FoldbackThermal ProtectionThe LTC4263 includes thermal overload protection in order to provide full device functionality in a miniature package while maintaining safe operating temperatures. Several factors create the possibility for very large power dissipation within the LTC4263. At port turn-on, while ILIM is active, the instantaneous power dissipated by the LTC4263 can be as high as 12W. This can cause 40ºC or more of die heating in a single turn-on sequence. Similarly, excessive heating can occur if an attached PD repeatedly pushes the LTC4263 into ILIM by drawing too much cur-rent. Excessive heating can also occur if the VDD5 pin is shorted or overloaded.The LTC4263 protects itself from thermal damage by monitoring die temperature. If the die temperature exceeds the overtemperature trip point, the LTC4263 removes port AC disconnect is an alternate method of sensing the pres-ence or absence of a PD by monitoring the port impedance. The LTC4263 forces an AC signal from an internal sine wave generator on to the port. The ACOUT pin current is then sampled once per cycle and compared to IACDMIN. Like DC disconnect, the AC disconnect sensing circuitry controls the tMPDO disconnect timer. When the connection impedance rises due to the removal of the PD, AC peak current falls below IACDMIN and the disconnect timer increments. If the impedance remains high (AC peak current remains below IACDMIN), the disconnect timer counts to tMPDO and the port is turned off. If the impedance falls, causing AC peak current to rise above IACDMIN for two consecutive samples before the maximum count of the disconnect timer, the timer resets and the port remains powered.The AC disconnect circuitry senses the port via the ACOUT pin. Connect a 0.47µF 100V X7R capacitor (CDET) and a 1kΩ resistor (RDET) from the DETECT pin to the port output as shown in Figure 8. This provides an AC path for sensing the port impedance. The 1kΩ resistor, RDET, limits current fl owing through this path during port power-on and power-off. An AC blocking diode (DAC) is inserted between the OUT pin and the port to prevent the AC signal from 4263fb
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LTC4263APPLICATIONS INFORMATION1A+ISOLATED48V SUPPLY0.1µF100VNC0.1µFLEDLTC4263VDD5500kCMLSH05-4DACRDET1kSMAJ58ASDVDD48OUTOUTACOUT4263 F08CPSE0.1µFX7R, 100VLEGACYMIDSPANPWRMGTVSSVSSOSCENFCLS–0.1µFCDET0.47µFX7R, 100VFigure 8. LTC4263 Using AC Disconnectbeing shorted by the LTC4263’s power control MOSFET. The 500kΩ resistor across DAC allows the port voltage to decay after disconnect occurs.Sizing of capacitors is critical to ensure proper function of AC disconnect. CPSE (Figure 8) controls the connection impedance on the PSE side. Its capacitance must be kept low enough for AC disconnect to be able to sense the PD. On the other hand, CDET has to be large enough to pass the signal at 110Hz. The recommended values are 0.1µF for CPSE and 0.47µF for CDET. The sizes of CPSE, CDET, and RDET are chosen to create an economical, physically compact and functionally robust system. Moreover, the complete Power over Ethernet AC disconnect system (PSE, transformers, cabling, PD, etc.) is complex; deviating from the recommended values of CDET, RDET and CPSE is strongly discouraged. Contact the Linear Technology Applications department for additional support.Internal 110Hz AC OscillatorThe LTC4263 includes onboard circuitry to generate a 110Hz (typ), 2VP-P sine wave on its OSC pin when a 0.1µF capacitor is connected between the OSC pin and VSS. This sine wave is synchronized to the controller inside the LTC4263 and should not be externally driven. Tying the OSC pin to VSS shuts down the oscillator and enables DC disconnect.Power-On Reset and Reset/Backoff TimingUpon startup, the LTC4263 waits four seconds before starting its fi rst detection cycle. Depending on the results of this detection it will either power the port, repeat detec-tion, or wait 3.2 seconds before attempting detection again if in midspan mode.The LTC4263 may be reset by pulling the SD pin low. The port is turned off immediately and the LTC4263 sits idle. After SD is released there will be a 4-second delay before the next detection cycle begins.VDD5 Logic-Level SupplyThe VDD5 supply for the LTC4263 can either be supplied externally or generated internally from the VDD48 supply. If supplied externally, a voltage between 4.5V and 5.5V should be applied to the VDD5 pin to cause the internal regulator to shut down. If VDD5 is to be generated inter-nally, the voltage will be 4.4V (typ) and a 0.1µF capacitor should be connected between VDD5 and VSS. Do not connect the internally generated VDD5 to anything other than a bypass capacitor and the logic control pins of the same LTC4263.LED Flash CodesThe LTC4263 includes a multi-function LED driver to inform the user of the port status. The LED is turned on when the port is connected to a PD and power is applied. If the port is not connected or is connected to a non-powered device with a 150Ω or shorted termination, the port will not be powered and the LED will be off. For other port conditions, the LTC4263 blinks a code to communicate the status to the user as shown in Table 3. One fl ash indicates low signature resistance, two fl ashes indicates high resistance, fi ve fl ashes indicates an overload fault, and nine fl ashes indicates that power management is preventing the port from turning on.4263fb16LTC4263APPLICATIONS INFORMATIONWhen active, the LED fl ash codes are repeated every 1.2 seconds. The duration of each LED fl ash is 75ms. Multiple LED fl ashes occur at a 300ms interval. The LTC4263 includes a feature for effi ciently driving the LED from a 48V power supply without the wasted power caused by having to drop over 45V in a current limit resistor. When operating the VDD5 supply internally, the LTC4263 drives the LED pin with a 6% duty cycle PWM signal. This allows use of the simple LED drive circuit in Figure 9 to minimize power dissipation. The modulation frequency of the LED drive is 28kHz, making the on period VDD48D110mH, 21mACOILCRAFTDS1608C-1062.2µs. During the 2.2µs that the LED pin is pulled low, cur-rent ramps up in the inductor, limited by RLED. Diode D2 completes the circuit by allowing current to circulate while the LED pin is open circuit. Since current is only drawn from the power supply 6% of the time, power dissipation is substantially reduced. When VDD5 is powered from an external supply, the PWM signal is disabled and the LED pin will pull down continu-ously when on. In this mode, the LED can be powered from the 5V supply with a simple series resistor.IEEE 802.3af COMPLIANCE AND EXTERNAL COMPONENT SELECTIONThis section discusses the other elements that go along with the LTC4263 to make an IEEE 802.3af compliant PSE. The LTC4263 is designed to control power delivery in IEEE 802.3af compliant Power Sourcing Equipment. Because proper operation of the LTC4263 also depends on external components and power sources like the 48V supply, using the LTC4263 in a PSE does not in itself guarantee IEEE 802.3af compliance. To ensure a com-pliant PSE design, it is recommended to adhere closely to the example application circuits provided. For further assistance contact the Linear Technology Applications department.D2BAS19RLED1kLEDVDD48LTC4263VDD5VSS4263 F090.1µFFigure 9. LED Drive Circuit with Single 48V SupplyTable 3. Port Status and LED Flash CodesPORT STATUSNon-Powered Device0Ω < RPORT < 200ΩPort OpenRPORT > 1MΩPort On25kΩLow Signature Resistance300Ω < RPORT < 15kΩHigh Signature Resistance33kΩ < RPORT < 500kΩPort Overload FaultPower Management Allocation ExceededLED FLASH CODEOffOffOn1 Flash2 Flashes5 Flashes9 FlashesFLASH PATTERNLED OffLED OffLED On 4263fb17LTC4263APPLICATIONS INFORMATION
Common Mode ChokesBoth non-powered and powered Ethernet connections achieve best performance for data transfer and EMI when a common mode choke is used on each port. For cost reduc-tion reasons, some designs share a common mode choke between two adjacent ports. This is not recommended. Sharing a common mode choke between two ports couples start-up, disconnect and fault transients from one port to the other. The end result can range from momentary noncompliance with IEEE 802.3af to intermittent behavior and even to excessive voltages that may damage circuitry in both the PSE and PD connected to the port.Transient Suppressor DiodeIEEE 802.3af Power over Ethernet is a challenging Hot Swap application because it must survive unintentional abuse by repeated plugging in and out of devices at the port. Ethernet cables could potentially be cut or shorted together. Consequently, the PSE must be designed to handle these events without damage.The most severe of these events is a sudden short on a powered port. What the PSE sees depends on how much CAT-5 cable is between it and the short. If the short oc-curs on the far end of a long cable, the cable inductance will prevent the current in the cable from increasing too quickly and the LTC4263 built-in short-circuit protection will control the current and turn off the port. However, the high current along with the cable inductance causes a large fl yback voltage to appear across the port when the MOSFET is turned off. In the case of a short occurring with a minimum length cable, the instantaneous current can be extremely high due to the lower inductance. The LTC4263 has a high-speed fault current limit circuit that shuts down the port in 20µs (typ). In this case, there is lower inductance but higher current so the event is still severe. A transient suppressor is required to clamp the port voltage and prevent damage to the LTC4263. An SMAJ58A or equivalent device works well to maintain port voltages within a safe range. A bidirectional transient suppressor should not be used. Good board layout places the transient suppressor between the port and the LTC4263 to enhance the protective function.If the port voltage reverses polarity and goes positive, the OUT pin can be overstressed because this voltage is stacked on top of the 48V supply. In this case, the transient sup-pressor must clamp the voltage to a small positive value to protect the LTC4263 and the PSE capacitor.Component leakages across the port can have an adverse affect on AC disconnect and even affect DC disconnect if the leakage becomes severe. The SMAJ58A is rated at less than 5µA leakage at 58V and works well in this applica-tion. There is a potential for stress induced leakage, so suffi cient margins should be used when selecting transient suppressors for these applications.4263fb
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LTC4263APPLICATIONS INFORMATION
CapacitorsSizing of both the CDET and CPSE capacitors is critical for proper operation of the LTC4263 AC disconnect sensing. See the AC Disconnect section for more information. Note that many ceramic capacitors have dramatic DC voltage and temperature coeffi cients. Use 100V or higher rated X7R capacitors for CDET and CPSE, as these have reduced voltage dependence while also being relatively small and inexpensive. Bypass the 48V supply with a 0.1µF, 100V capacitor located close to the LTC4263. The VDD5 supply also requires a 0.1µF bypass capacitor.FuseWhile the LTC4263 does not require a fuse for proper operation or for compliance with IEEE 802.3af, some safety requirements state that the output current must be limited to less than 2A in less than 60 seconds if any one component fails or is shorted. Since the LTC4263 is the primary current limiter, its failure could result in excess current to the port. To meet these safety requirements, a fuse can be placed in the positive leg of the port. The fuse must be large enough that it will pass at least 450mA when derated for high temperature but small enough that it will fuse at less than 2A at cold temperature. This requirement can usually be satisfi ed with a 1A fuse or PTC. Placing the fuse between the RJ-45 connector and the LTC4263 and its associated circuitry provides additional protection for this circuitry. Consult a safety requirements expert for the application specifi c requirements.Power SupplyPoor regulation on the 48V supply can lead to noncompli-ance. The IEEE specifi cation requires a PSE output voltage between 44V and 57V. When the LTC4263 begins powering an Ethernet port, it controls the current through the port to minimize disturbances on VSS. However, if the VSS supply is underdamped or otherwise unstable, its voltage could go outside of the IEEE-specifi ed limits, causing the PSE to be noncompliant. This scenario can be even worse when a PD is unplugged because the current can drop immediately to zero. In both cases the port voltage must always stay between 44V and 57V. Beyond this, the IEEE 802.3af specifi cation places specifi c ripple, noise and load regulation requirements on the PSE. Disturbances on VSS can also adversely affect detection, classifi cation and AC disconnect sensing. For these reasons, proper bypassing and stability of the VSS supply is important.Another problem that can affect the VSS supply is insuf-fi cient power, leading to the supply voltage dropping out of the specifi ed range. The 802.3af specifi cation states that if a PSE powers a PD it must be able to provide the maximum power level requested by the PD based on the PD’s classifi cation. The specifi cation does allow a PSE to choose not to power a port, typically because the PD requires more power than the PSE has available to deliver. If a PSE is built with a VSS supply not capable of deliver-ing full power to all ports, it is recommended to use the LTC4263 power management feature to prevent ports from being turned on when there is insuffi cient power. Because the specifi cation also requires the PSE to sup-ply an inrush current of 400mA at up to a 5% duty cycle, the VSS supply capability should be at least a few percent higher than the maximum total power the PSE needs to supply to the PDs. 4263fb
19
LTC4263APPLICATIONS INFORMATION
Isolation The IEEE 802.3af standard requires Ethernet ports to be electrically isolated from all other conductors that are user accessible. This includes the metal chassis, other connec-tors, and the AC power line. Environment A isolation is the most common and applies to wiring within a single building serviced by a single AC power system. For this type of application, the PSE isolation requirement can be met with the use of a single, isolated 48V supply powering several LTC4263 ports. Environment B, the stricter isola-tion requirement, is for networks that cross an AC power distribution boundary. In this case, electrical isolation must be maintained between each port in the PSE. The LTC4263 can be used to build a multi-port Environment B PSE by powering each LTC4263 from a separate, isolated 48V supply. In all PSE applications, there should be no user accessible connections to the LTC4263 other than the RJ-45 port.4263fb
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LTC4263TYPICAL APPLICATIONSThree Port Midspan PSE with Power Management Set for 30WISOLATED48V0.1µF100V14120.1µF231356LTC4263VDD5SDMIDSPANENFCLSVSSVSSVDD48LEDOSCACOUTOUTOUT1114781090.1µF100V1kMIDSPANIN12345678RJ45SMAJ58AMIDSPANOUT12345678RJ45LEGACYPWRMGTMIDSPANIN0.1µF100V14120.1µF231356LTC4263VDD5SDMIDSPANENFCLSVSSVSSVDD48LEDOSCACOUTOUTOUT1114781090.1µF100VSMAJ58A1k12345678RJ45MIDSPANOUT12345678RJ45LEGACYPWRMGTMIDSPANIN0.1µF100V14120.1µF231356LTC4263VDD5SDMIDSPANENFCLSVSSVSSVDD48LEDOSCACOUTOUTOUT1114781090.1µF100VSMAJ58A4263 TA02MIDSPANOUT12345678RJ451kLEGACYPWRMGT12345678RJ45RPM7.15k1%CPM1µF4263fb21LTC4263PACKAGE DESCRIPTIONDE Package14-Lead Plastic DFN (4mm × 3mm)(Reference LTC DWG # 05-08-1708 Rev A)0.70 ±0.053.60 ±0.051.70 ±0.052.20 ±0.05(2 SIDES)PACKAGEOUTLINE0.25 ± 0.050.50BSC3.30 ±0.05(2 SIDES)RECOMMENDED SOLDER PAD PITCH AND DIMENSIONS4.00 ±0.10(2 SIDES)R = 0.05TYPR = 0.115TYP8140.40 ± 0.103.00 ±0.10(2 SIDES)PIN 1TOP MARK(SEE NOTE 6)1.70 ± 0.05(2 SIDES)PIN 1 NOTCHR = 0.20 OR0.35 × 45°CHAMFER (DE14) DFN 0905 REV A70.200 REF0.75 ±0.053.30 ±0.05(2 SIDES)10.25 ± 0.050.50 BSC0.00 – 0.05BOTTOM VIEW—EXPOSED PADNOTE:1. DRAWING PROPOSED TO BE MADE VARIATION OF VERSION (WGED-3) IN JEDECPACKAGE OUTLINE MO-2292.DRAWING NOT TO SCALE 3. ALL DIMENSIONS ARE IN MILLIMETERS4. DIMENSIONS OF EXPOSED PAD ON BOTTOM OF PACKAGE DO NOT INCLUDE MOLD FLASH. MOLD FLASH, IF PRESENT, SHALL NOT EXCEED 0.15mm ON ANY SIDE5. EXPOSED PAD SHALL BE SOLDER PLATED6. SHADED AREA IS ONLY A REFERENCE FOR PIN 1 LOCATION ON THE TOP AND BOTTOM OF PACKAGE4263fb22LTC4263PACKAGE DESCRIPTIONS Package14-Lead Plastic Small Outline (Narrow .150 Inch)(Reference LTC DWG # 05-08-1610).045 ±.005 .050 BSCN1413.337 – .344(8.560 – 8.738)NOTE 312111098.245MINN.160 ±.005.228 – .244(5.791 – 6.197)123N/2N/2.150 – .157(3.810 – 3.988)NOTE 3.030 ±.005 TYPRECOMMENDED SOLDER PAD LAYOUT1234567.010 – .020× 45°(0.254 – 0.508).008 – .010(0.203 – 0.254)0° – 8° TYP.053 – .069(1.346 – 1.752).004 – .010(0.101 – 0.254).016 – .050(0.406 – 1.270)NOTE:1. DIMENSIONS IN .014 – .019(0.355 – 0.483)TYP.050(1.270)BSCINCHES(MILLIMETERS)2. DRAWING NOT TO SCALE3. THESE DIMENSIONS DO NOT INCLUDE MOLD FLASH OR PROTRUSIONS. MOLD FLASH OR PROTRUSIONS SHALL NOT EXCEED .006\" (0.15mm)S14 05024263fbInformation furnished by Linear Technology Corporation is believed to be accurate and reliable. However, no responsibility is assumed for its use. Linear Technology Corporation makes no representa-tion that the interconnection of its circuits as described herein will not infringe on existing patent rights.23LTC4263TYPICAL APPLICATIONComplete Single-Port Endpoint PSE with Integrated RJ45J11TD+ISOLATED48V7CTC30.1µF100VD1BAS19L110mH, 21mADS1608C-106COILCRAFT9RD–1:1R61kC7, 0.47µF100V, X7RC50.1µFD2SMAJ58AF11AC40.1µF100V510611VC1AVC1BVC2AVC2B2kV1000pFRX–5722nF22nF22nF22nF757575758LED1LN1351C-TRGRNPHYTX+18TD–2RD+1:1TX–RX+23OUT TO CABLEU1LTC426311VDD48114LEDVDD5412PWRMGTSD72OSCLEGACY3MIDSPAN813ACOUTENFCLS105VSSOUT96VSSOUTR21kC10.1µFCMLSHO5-4D5R5510kJKO-0044PULSE4263 TA03RELATED PARTSPART NUMBERLTC1737LTC3803LTC4257LTC4257-1LTC4258LTC4259A-1LTC4267DESCRIPTIONHigh Power Isolated Flyback ControllerCurrent Mode Flyback DC/DC Controller in ThinSOTTMIEEE 802.3af PD Interface ControllerIEEE 802.3af PD Interface ControllerQuad IEEE 802.3af Power Over Ethernet ControllerQuad IEEE 802.3af Power Over Ethernet ControllerIEEE 802.3af PD Interface with SwitcherCOMMENTSSense Output Voltage Directly from Primary-Side Winding200kHz Constant-Frequency, Adjustable Slope Compensation,Optimized for High Input Voltage Applications100V 400mA Internal Switch, Programmable Classifi cation100V 400mA Dual Current LimitDC Disconnect OnlyWith AC DisconnectIntegrated Current Mode Switching RegulatorThinSOT is a trademark of Linear Technology Corporation. 4263fb24Linear Technology CorporationLT 0307 REV B • PRINTED IN USA
1630 McCarthy Blvd., Milpitas, CA 95035-7417 (408) 432-1900 ● FAX: (408) 434-0507 ● www.linear.com© LINEAR TECHNOLOGY CORPORATION 2006
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